Novel Chip Architecture Could Extend Moore's Law

Hewlett-Packard researchers have designed a faster, more energy-efficient chip by packing in more transistors--without shrinking them.

These nanoscale crossbars, developed at HP, could lead to an entirely new chip architecture that would improve chip performance without shrinking transistors. The crossbars are to be placed on top of the transistors, replacing the wire interconnects currently found between them and freeing up space for more transistors. Credit: Hewlett-Packard Company

In the chip-making industry, the best way to increase the speed of electronics and make them cheaper has always been to shrink a chip's transistors to create room for more. But now researchers at Hewlett-Packard (HP) Labs have announced a radically different approach: a design that creates room for eight times more transistors on a chip, while avoiding the need to make the transistors smaller.

"For a long time, we in the industry have been obsessed with this idea that higher capacity [chips] and lower cost equals smaller transistors, and we've been investing the bulk of our efforts in this area," says Stanley Williams, senior fellow and director of quantum-science research at HP Labs. The new research, Williams says, "is the first proof that it's possible to dramatically improve integrated circuits without shrinking transistors."

Chip components have steadily gotten smaller since the 1960s, following Moore's Law: the prediction that approximately every two years, integrated circuits will double in transistor capacity and speed. However, engineers know that transistor size will reach its physical limit within the next decade or so. HP's new design could extend Moore's Law years beyond that, says Williams.

The problem with today's chip architecture is that a large percentage of silicon isn't actually used for transistors. Instead, much of the silicon real estate is populated with aluminum-wire interconnects that supply power and instructions to the circuit. So to make room for more transistors, Williams and HP researcher Greg Snider designed a chip with the wires on top, instead of between transistors. The research will be published in the January 24 issue of Nanotechnology.

This top layer of wiring is based on a "crossbar" structure--a sort of nanoscale wire mesh--that researchers at HP Labs have been developing for molecular memory devices since the 1990s. At each junction in the mesh, Williams says, is a switch that controls the flow of electrons to and from the transistor beneath it.

The HP work follows research done by Konstantin Likharev, professor of physics at Stony Brook University, in New York, who first proposed connecting wires atop transistors. However, Likharev's scheme required atomic manipulation of the nanowires--a manufacturing impossibility, says Williams. In contrast, says Williams, HP's design has the potential to be easily integrated into a chip-making facility.

Currently, HP researchers are developing a laboratory prototype using the design, and Williams expects it to be complete by the end of the year. By 2010, he says, the technology should be ready for manufacturing.

The first application of the technology will most likely be in a type of chip called field-programmable gate arrays (FPGAs), which have the flexibility to be programmed to complete a variety of tasks. FPGAs are typically used in the design stages of electronics and communication systems. However, once the bugs are worked out of the design, manufacturers replace FPGAs with faster, cheaper chips called application-specific integrated circuits (ASICs). Reducing the size and cost of FPGAs and increasing their speed has the potential to shift the balance between FPGAs and ASICs, says Williams.

"Reducing the size and cost of FPGAs and increasing their speed has the potential to shift the balance between FPGAs and ASICs, says Williams."

Don't forget power...the power spike when an FPGA configures is rather bad. Also, FPGAs tend to burn a lot of power when they're simply sitting there and doing nothing (FPGAs are mostly SRAM...the most primitive element of an FPGA is either a 4 or 6 input lookup table that allows you to implement any 4 or 6 input logic function).

Another neat FPGA trick is to embed an x4 PCI Express core and light cigarettes off the ridiculously hot chip. However, despite the flaws, I still love designing for these devices...too much fun :) !!!! Moreover, this tends to aggravate the anti-smoking crowd, so don't try that at home.

This crossbar connect seems to help routing significantly (which helps speed drastically) as well as transistor density. Once you cross below the .25u node, the delays on the wires are actually larger than the time it takes for a logic gate to flip in most cases! This looks pretty slick...just like copper interconnect was a few years ago!

The best applications for FPGAs is recreating the hardware of old video games...on a pet project I have here at home, I can configure the chip to be the Atari 2600 one minute, and Colecovision the next...you can do this with software emulation, but hardware solutions just look better :) :)!!!

FPGA prices have plummeted over the past 5 years while the densities have increased significantly....hopefully we can see these devices penetrate the consumer market thus creating more work for me in the future as well as move me to Florida sooner rahter than later :-P.

From CNET:

Can HP fool Moore's Law?

************************AN EXCERPT ******************************

At the crossbar
The crossbar is one of the more prominent ideas to emerge from HP Labs in the past several years. The company has demonstrated how the structure can be used to improve memory chips, compensate for manufacturing defects and help circuits do calculations.

Although HP has largely exited the chip business, it has put more emphasis on gaining revenue from licensing technology. If the crossbar concept were to take off, HP could gain millions of dollars in royalties.

So far, the company has created a simulation of a field-programmable gate array (FPGA) with a crossbar grid, and it hopes to have a prototype by the end of the year, Williams said. By 2010, manufacturers may be able to incorporate the crossbar communications system into commercial chips.

Eventually, it's possible that the concept could be incorporated into other types of chips. Many analysts already predict that the copper interconnects that supplanted aluminum in the 1990s will themselves have to get replaced.

Williams and HP's Greg Snider are studying the concept with an FPGA, which is a chip that can be programmed for many different functions, in part because that's where the greatest gains could be found. In an FPGA, different functional blocks are wired directly to each other through interconnects, sort of like an old-fashioned intercom system.

As a result, any increase in the functional blocks in an FPGA leads to a geometric increase in the number of data pathways.

"In an FPGA, all of the communications stuff can take up 80 percent of the chip area," Williams said.

The crossbar system would eliminate the static plumbing in traditional chips with an intelligent communications system that would only connect functional blocks when they needed to be connected. (Some of the HP Labs work relies on earlier research from Stony Brook University in New York.)

Size matters
The potential benefits could be numerous. With a dynamic communications network, certain functional blocks or transistor areas could be put to sleep when not in use, thereby cutting power. Manufacturers could also salvage troubled multicore chips by circumventing flawed circuitry.

"You don't have to consign it to the junk heap because of one bad transistor," Williams said.

HP estimated that an FPGA made with 45-nanometer transistors and a grid of nanowires measuring 4.5 nanometers across would be only 4 percent as large as a standard FPGA made on the 45-nanometer process. (Chips built on that 45-nanometer process are expected to come out at the end of this year. The nanometer measurement refers to the average feature size on a chip. A nanometer is a billionth of a meter.) The clock speed on the hypothetical chip would be slower, but the amount of energy consumed per calculation would be lower.

Now on News.com:

The crossbar structure itself could be made out of aluminum or copper nanowires that are smaller than today's interconnects. The shrinkage problem would also be addressed with the adoption of a new process called imprint lithography.

In traditional lithography, a light beam is used to "draw" a trench in silicon. The trench then gets dug out through chemical processes and filled with aluminum. Imprint lithography looks like it sounds: a mold is pressed into treated silicon, and the resulting imprint is then filled with metal.

The imprint creates smaller lines than traditional lithography, but it hasn't yet been adopted on a mass scale. The technique works best when the circuit lines are fairly regular, and that ties in with HP's crossbar work: the crossbar grid consists of two layers of parallel wires at 90 degree angles.

Hard-drive makers are thinking of adopting the imprint technique for creating patterns in future hard-drive media.

The paper will come out in the January 24 edition of Nanotechnology, and HP is hoping to make a splash.

"We think that is a fairly big deal," Williams said.

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