Skip to comments.Power7+ chips debut in fat IBM midrange systems
Posted on 10/04/2012 9:26:39 AM PDT by Ernest_at_the_Beach
IBM has taken the wraps off the first of its Power Systems machinery to make use of its cache-heavy Power7+ processors, and as El Reg anticipated from the hints in the announcement invitation put out two weeks ago, Big Blue is starting near the top of the line as it upgrades systems that run AIX, IBM i (formerly known as OS/400), and Linux.
As has been the case for the past several generations, the rollout for the Power7+ chips will be a gradual one. "The rest of the products will get the Power7+ next year, with the exception of the Power 795," Steve Sibley, director of worldwide product management for IBM's Power Systems division, tells El Reg. "Just like with the Power 595, we already built the fastest processor and I/O into that machine."
It's tough to argue with the guy in charge of the product line but it's not impossible. Even if IBM can't crank up the clock speed of the 3.7GHz and 4GHz processors used in the high-end, 32-socket Power 795 machine,, the ability to have processors with 2.5 times the L3 cache per core (at 10MB) and better sleep states and Turbo Core modes would no doubt be of use to more than a few Power 795 shops.
If enough customers ask for such a thing, you can bet IBM will sell 'em. Just because Big Blue didn't do it before doesn't mean it can't do it now.
The eight-core Power7+ processor was previewed at the end of August at the Hot Chips 24 chippery fest, and we gave you a peek into its expected performance in the wake of the tech presentation, along with some thoughts on the overclocking potential for the Power7+ chip.
(Excerpt) Read more at theregister.co.uk ...
The Power7+ chip has a lot of new features to help accelerate specific functions inside of Power System boxes, including on-chip memory compression, encryption, and hashing algorithms, as well as a random-number generator that cannot be predicted because it is based on random electronic effects on the chip.
The Power7+ chip is implemented in a 32-nanometer process. Specifically, IBM's wafer bakery in East Fishkill, New York, uses a copper/silicon-on insulator process with high-k metal gates to etch the Power7+ chips, which have 2.1 billion transistors on the die.
The shrink from 45 to 32 nanometers allows Big Blue to put 80MB of L3 cache on the die, plus a slew of accelerators.
It is becoming possible to have more and more cache on-chip. I predict L3 cache will just merge with general-purpose RAM soon. The marginal improvement in performance from general-purpose DRAM to on-chip L3 cache is shrinking rapidly.
using the AIX memory compression that debuted with AIX 7.1 running on Power7 chips, you could get as much as 2X the usable main memory, but by using the two on-chip accelerators that IBM put on the Power7+ chip to run the proprietary compression algorithm for AIX memory compression, you can get up to 2.25X usable main memory and not have the overhead of running the compression algorithms on the Power7+ cores. You get the double benefit of more addressable main memory (4TB can look like 9TB) as well as lower CPU core overhead, allowing the central processors to do more work.
The accelerators, by the way, are in the uncore area of the Power7+ chips and shared by the cores.
All kinds of little tricks are possible ....
Looks great. I’ll take a dozen to beef up my workstation, along with a couple hundred gigs of ram.
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