Yes those of us in RTL VHDL or Verilog land know how to do it. That's why we get the big bucs.
The problem is the average app coder is lazy and just wants it to work so they can get paid, they have no clue of what they are doing.
So here is an interesting question how many cores is your compiler using, be careful, how many did you pay to have unlocked?
“So here is an interesting question how many cores is your compiler using, be careful, how many did you pay to have unlocked?”
I don’t understand the question :-) ... Xilinx does a good job using multiple cores during mapping and place and route. I can enable 2 cores during the mapper, up to 4 during place and route (I might have that reversed ...)
OK, I think I see your question :-). My machine at work is a 4 core Xeon, so I paid for 4 cores and have been using all of them from day one :-) . I usually have two running during builds, one open for simulations (I use Modelsim PE ... no parallelism or 64 bit support ... it’s torture), and one open for “other stuff”.
Prior to that, I had some kind of quad core Intel processor back before Xilinx supported multicore builds. Yes, in that case, I had two cores idle most of the time :-). So I paid for 4, but only used two most of the time. One core for work, the other for Free Republic, I mean, “other stuff” :-). The others mainly sat idle.
We’re actually exploiting the two ARM CPU cores in a Zynq right now FWIW (not just OS scheduling processes ... I mean real parallel processing stuff :-) )
I do most of the hardware acceleration for our fairly complex algorithms. I’m trying to get back into the software world somewhat just to get a better feel for other stuff that might benefit from hardware acceleration ... I’ve grown tired of beating back software people that seem to want their main program to be an initialization routine while the logic does everything else :-).
I’m going to be building a new Haswell-E system for home/contracting use ... I went the 6 core, 3.5GHz route for that.
Again, I certainly see your point, but I’m also seeing software people get a LOT better using multiple CPUs ... I don’t think it’s a lot of hype anymore (it certainly was not too long ago).
“So here is an interesting question how many cores is your compiler using, be careful, how many did you pay to have unlocked?”
I don’t understand the question :-) ... Xilinx does a good job using multiple cores during mapping and place and route. I can enable 2 cores during the mapper, up to 4 during place and route (I might have that reversed ...)
OK, I think I see your question :-). My machine at work is a 4 core Xeon, so I paid for 4 cores and have been using all of them from day one :-) . I usually have two running during builds, one open for simulations (I use Modelsim PE ... no parallelism or 64 bit support ... it’s torture), and one open for “other stuff”.
Prior to that, I had some kind of quad core Intel processor back before Xilinx supported multicore builds. Yes, in that case, I had two cores idle most of the time :-). So I paid for 4, but only used two most of the time. One core for work, the other for Free Republic, I mean, “other stuff” :-). The others mainly sat idle.
We’re actually exploiting the two ARM CPU cores in a Zynq right now FWIW (not just OS scheduling processes ... I mean real parallel processing stuff :-) )
I do most of the hardware acceleration for our fairly complex algorithms. I’m trying to get back into the software world somewhat just to get a better feel for other stuff that might benefit from hardware acceleration ... I’ve grown tired of beating back software people that seem to want their main program to be an initialization routine while the logic does everything else :-).
I’m going to be building a new Haswell-E system for home/contracting use ... I went the 6 core, 3.5GHz route for that.
Again, I certainly see your point, but I’m also seeing software people get a LOT better using multiple CPUs ... I don’t think it’s a lot of hype anymore (it certainly was not too long ago).