Posted on 02/11/2007 4:36:27 PM PST by xcamel
With no Spring Intel Developer Forum happening this year in the US, we turn to the International Solid-State Circuits Conference (ISSCC) for an update on Intel's ongoing R&D projects. Normally we'd hear about these sorts of research projects on the final day of IDF, these days presented by Justin Rattner, but this year things are a bit different. The main topic at hand today is one of Intel's Tera-scale computing projects, but before we get to the chip in particular we should revisit the pieces of the puzzle that led us here to begin with.
[snip]
Justin Rattner's keynotes talked about some of Intel's Tera-scale projects, with 3D die stacking delivering terabytes of bandwidth needed for the next decade of CPUs and silicon photonics enabling terabits of I/O for connecting these CPUs to the rest of the system. The final vector that Rattner spoke about, was delivering a teraflop of performance. The CPU Rattner spoke of was a custom design by Intel that featured 80 cores on a single die, and today Intel revealed a lot more about its Teraflop CPU, the architecture behind it and where it fits in with the future of Intel CPUs.
[snip]
The Chip
As its name implied, the Teraflops Research Chip is a research vehicle and not a product. Intel has no intentions of ever selling the chip, but technology used within the CPU will definitely see the light of day in future Intel chip designs.
The Teraflops chip is built on Intel's 65nm process and features a modest, by today's standards, 100M transistors on a 275mm^2 die. As a reference point, Intel's Core 2 Duo, also built on a 65nm process, features 291M transistors on a 143mm^2 die. The reason the Teraflops chip is large given its relatively low transistor count is that there's very little memory on the chip itself, whereas around half of Intel's Core 2 is made up of L2 cache. Other than being predominantly logic circuits, the Teraflops chip also has a lot of I/O circuitry on it that can't be miniaturized as well as most other circuits resulting in a larger overall chip size. The chip features 8 metal layers with copper interconnects.
The Teraflops chip is built on a single die composed of 80 independent processor cores, or tiles as Intel is calling them. The tiles are arranged in a rectangle 8 tiles across and 10 tiles down; each tile has a surface area of 3mm^2.
The chip uses a LGA package like Intel's Core 2 and Pentium 4 processors, but features 1248 pins. Of the 1248 pins on the package, 343 of them are used for signaling while the rest are predominantly power and ground.
Much more: http://anandtech.com/cpuchipsets/showdoc.aspx?i=2925
1248 pins? The bottoms of CPUs are going to start looking like they're covered in stiff fur ...
that would be socket "F"
/sarc
Cool.I wonder if Moores Law now means that every 18 months we will see a doubling of cores instead of speed.
AMd has a 1207 pin chip out, so 1248 isnt that unreasonable.
"1248 pins? The bottoms of CPUs are going to start looking like they're covered in stiff fur ..."
If that quantum PC from Canada actually works like they say Intel is toast.
Aww the LGA, thats are one of the better chip upgrades for consumers in a long time, cant tell you the number of times I have had to sit and restraighten a pin only to have it break on me....but that was back in the 90's.Pins today seem to be stronger.
I sure hope that, by then, software will have been developed to use 80 cores. Right now, I have a 2-core system, and they are mainly idle (well, they do scientific research).
I like my dual opteron 280's - they get lots of "scientific work" done
We'll probably have to use Beowulf software to control it. :-)
Then again, you could have a Beowulf cluster of the 80 core systems and have exoflops of computation available in a single rack of computers.
Makes my head hurt to even think about it.
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