The current x86 products today aren’t CISC any more. They have so many transistors available that what is really happening is that the chip is translating the x86 instructions in your software into what Intel calls “micro-ops” before issuing them further - effectively converting CISC to RISC. Much of the internal P6 (and later) architecture is about the RISC portion of the execution engine(s) in the chip. At the internal micro-architecture level, the current Intel products are much more RISC than they are CISC, but they pulled a very smart move in putting a translation engine on top of their micro-architecture to preserve the customer’s software-for-CISC investment. This is the one reason why Intel now dominates the CPU market, and the “true RISC” vendors now have to look to embedded markets for their survival.
A true CISC processor would be like the original Pentiums. Today, I can’t think of any true CISC-on-a-chip platform left out there - every chip architecture out there is a tantamount admission that RISC won the architecture fight, with large caches (or “register files” in original RISC lingo) operating at CPU clock speeds 1:1, speculative execution, one (or more) instructions issuing per clock, deep pipelines, branch prediction, speculative execution, etc.
Out-of-order execution isn’t a RISC concept, so we can’t claim that’s an admission of RISC wins, but it also sure as heck isn’t a CISC feature either.
In the end, CISC architectures are no more. Things like the S/370, VAX, DG’s Eclipse, National’s 32xxx, etc - all done and gone.
But then looking at the market, we have to ask “What happened to ‘true RISC’ architectures like SPARC (and MIPS, and, and, and...) ?”
Simple. Unix (and all its variants) became wildly popular on x86 chips. Once you’re talking of one Unix vs. the next one (eg, Solaris vs. Linux, BSD, OS X, etc), are you willing to pay a premium for the SPARC architecture vs. the latest commodity x86 platform? Nope. What does SPARC give you that the latest commodity x86 chipset doesn’t? Maybe better virtual memory support - but nothing that the user will see. SGI used to be able to flog their graphics performance over the “Unix on a x86 box” alternative - and they lost. Today, SGI has pretty much given up on the MIPS, and SGI is pretty much done in workstations as well.
Microcoding is a very old idea which was inherently RISC. I guess you’re really talking about the amount of chip real estate dedicated to RISCesque architecture (as we know it in the latter day). Big buffers, big pipe lines, etc.
Easiest way to say it: Modern x86 is a RISC chip with a CISC front-end.